In the field of semiconductor integrated circuit (IC) manufacturing, active semiconductor devices, e.g. transistors, are generally manufactured or formed by applying well-known front end of line (FEOL) technologies. A transistor may be a field-effect-transistor (FET), e.g. a complementary metal-oxide-semiconductor (CMOS) FET, and the FET may be a p-type doped FET (pFET) or an n-type doped FET (nFET). Different types of transistors may be manufactured on a common substrate of semiconductor chip or structure.
One approach for improving semiconductor performance is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing an appropriate strain/stress into the Si lattice of the silicon (Si)-containing substrate that is used to fabricate the semiconductor device into the finished product of an integrated circuit.
The application of stress along the channel changes the lattice dimensions of the silicon (Si)-containing substrate that is used to fabricate the semiconductor device. By changing the lattice dimensions, the band structure and mobility of the material are changed as well.
In most recent several years, efforts of continuing to scale FET devices have been mainly focused on the area of stress engineering. For example, in the case of manufacturing pFET devices, incorporation of compressive stress liners and/or stressors of embedded SiGe (eSiGe) in source and drain regions have successfully demonstrated improvement in performance of the pFET devices.
In order to further enhance performance of the pFET devices, it is desirable to develop new techniques involving the use of eSiGe in semiconductor fabrication.